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Espressif Systems /ESP32-P4 /SPI0 /SPI_MEM_SRAM_CLK

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Interpret as SPI_MEM_SRAM_CLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0SPI_MEM_SCLKCNT_L0SPI_MEM_SCLKCNT_H0SPI_MEM_SCLKCNT_N0 (SPI_MEM_SCLK_EQU_SYSCLK)SPI_MEM_SCLK_EQU_SYSCLK

Description

SPI0 external RAM clock control register

Fields

SPI_MEM_SCLKCNT_L

For SPI0 external RAM interface, it must be equal to spi_mem_clkcnt_N.
SPI_MEM_SCLKCNT_H

For SPI0 external RAM interface, it must be floor((spi_mem_clkcnt_N+1)/2-1).
SPI_MEM_SCLKCNT_N

For SPI0 external RAM interface, it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)
SPI_MEM_SCLK_EQU_SYSCLK

For SPI0 external RAM interface, 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data